This invention relates to nonvolatile semiconductor memories and more particularly to a flash Electrically Erasable and Programmable Read Only Memory (EEPROM) that employs both single-bit and multi-bit memory cell arrays. This invention also relates to the method of performing data operations within the flash EEPROM.
Because of their advanced performance characteristics, including higher programming speeds and lower power consumption, high density nonvolatile memories, particularly flash EEPROMs, have recently proven useful as mass storage devices (or storage media) for portable electronic devices (such as digital still cameras and memory cards) and hard disks in personal computers, among other things. Flash memories are classified into two types, namely, a NAND-type and a NOR-type, in accordance with the logical configuration of the memory cells within the memory. In the NOR-type flash memory, each of the memory cells is connected to a corresponding word line and bit line and is independent of adjacent memory cells. In the NAND-type flash memory, however, each string (which contains multiple memory cells), as opposed to each memory cell individually, is connected to a corresponding bit line through a bit-line contact. Consequently, the NOR-type flash memory requires a greater number of contacts in order to couple the bit lines and memory cells together than the NAND-type flash memory. The NAND-type flash memory is therefore superior to the NOR-type flash memory in integration density.
Industry desires for more efficient integration density in a flash memory and for expanded memory capacity have led to the development of multi-bit (also known as multi-level, multi-state, or multiple bit) technology, wherein a plurality of bits are stored within a single memory cell. By providing for the storage of multiple bits within each memory cell, multi-bit technology contributes to a reduction in the cost-per-bit of data storage in flash memories that employ this technology. One prior art multi-bit configuration is disclosed on pp. 132-133 of the ISSC Digest of Technical Papers dated February 1995, in an article entitled "A Multilevel-Cell 32 Mb Flash Memory," written by M. Bauer, et al. Specifically, this article discloses a cell array arranged in the NOR-type flash memory configuration in which a memory cell uses two bits to store one of four data states, i.e., "00", "01", "10", and "11". Each of these four states corresponds to a unique voltage level, e.g., "00"=2.5V, "01"=1.5V, "10"=0.5V, and "11"=-3V. These voltage levels are threshold values assigned to allow data to be read from a memory cell having one of these four states of data stored therein. Significantly, the memory cell contains a distribution profile corresponding to these various threshold values. Furthermore, memory cells coupled to a single word line can have threshold voltages that differ from each other.
To detect the data state of a memory cell, a read voltage having a voltage level interposed between two threshold voltage levels, or positioned on a lower or higher side of a threshold voltage, must be applied to a gate of each of the memory cells through a word line coupled thereto. Unfortunately, the width between adjacent threshold voltages (hereinafter referred to as a "window") is less than that found in a normal (i.e., single-bit) flash memory. For example, the window in a four-state flash memory is about 0.6V. Furthermore, when a word line voltage for performing a reading operation is located in a window of about 0.6V, the margin between an edge of the threshold voltage profile and the level of the word line voltage may not be more than approximately 0.3V (as opposed to about a 1.3V margin in a single-bit memory). Therefore, when multi-bit flash memories are made using a manufacturing process subject to variations or when they are influenced by variations in word line voltage level and temperature, the probability of having invalid sensing operations becomes significant. This weak immunity against variations in external conditions suggests that the utility of the multi-bit flash memory as a storage device is limited to the storage of mass information, such as audio data, for example, where the failure to store even several data bits does not significantly disturb the organization of the information as a whole. Until now, therefore, single-bit flash memories have been used for storing information where reliability and stability of data storage are important, such as in the Basic Input/Output System (BIOS) or for font storage.
Despite the well-known respective advantages of both the single-bit and the multi-bit flash memories, these two types of flash memories have traditionally been fabricated on separate semiconductor chips. Therefore, the prior art semiconductor chips may only perform either the single-bit or the multi-bit operations within the memory cells of the chip, depending upon the configuration chosen during fabrication.
FIG. 1 shows a block diagram of a memory array and data field arranged in a conventional flash memory. A cell array region of the conventional flash memory, as shown in FIG. 1, is divided into two portions; namely, a memory array 10, containing memory sectors, and a device data field 20, containing data sectors corresponding to the memory sectors. Each memory sector includes a normal memory array and a redundant array. The normal memory array is used to store data. The redundant memory array can be substituted for bad portions of the normal memory array within the same sector. Each data sector retains general information about a corresponding memory sector, including such information as the locations of bad sectors in the normal memory array, and an address mapping for data formulation or substitution. Because the data stored in the device data field 20 is extremely important for determining whether an access operation of the memory data is either valid or invalid, the device data field 20 should be located in a stable single-bit retention environment, rather than in an unstable multi-bit retention area, in order to guarantee data stability.
The industry is therefore in need of a flash memory consisting of both single-bit and multi-bit memory cell arrays on a single semiconductor chip, so that important memory information can be reliably stored in a single-bit area, while less critical mass information can be stored in the more highly integrated multi-bit areas. Such a configuration can provide for both the necessary address mapping integrity and the general memory cell information while also providing greater memory capacity in a smaller chip size.